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 FQS4410
May 2000
QFET
FQS4410
Single N-Channel, Logic Level, Power MOSFET
General Description
These N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for low voltage applications such as DC/DC converters, high efficiency switching for power management in portable and battery operated products.
TM
Features
* * * * * * 10A, 30V, RDS(on) = 0.0135 @VGS = 10 V Low gate charge ( typical 21 nC) Low Crss ( typical 145 pF) Fast switching Improved dv/dt capability 175C maximum junction temperature rating
8 7 6 5
4 3 2 1
Absolute Maximum Ratings
Symbol VDSS ID IDM VGSS dv/dt PD TJ, TSTG
TC = 25C unless otherwise noted
Parameter Drain-Source Voltage - Continuous (TC = 25C) Drain Current - Continuous (TC = 70C) Drain Current - Pulsed
(Note 1)
FQS4410 30 10 8 50 20 7.0 2.5 0.02 -55 to +175
Units V A A A V V/ns W W/C C
Gate-Source Voltage Peak Diode Recovery dv/dt Power Dissipation (TC = 25C) Linear Derating Factor Operating and Storage Temperature Range
(Note 3)
Thermal Characteristics
Symbol RJA Parameter Thermal Resistance, Junction-to-Ambient Typ -Max 50 Units C/W
(c)2000 Fairchild Semiconductor International
Rev. A, May 2000
FQS4410
Electrical Characteristics
Symbol Parameter
TC = 25C unless otherwise noted
Test Conditions
Min
Typ
Max
Unit s
Off Characteristics
BVDSS BVDSS / TJ IDSS IGSSF IGSSR Drain-Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse VGS = 0 V, ID = 250 A ID = 250 A, Referenced to 25C VDS = 30 V, VGS = 0 V VDS = 24 V, TC = 125C VGS = 20 V, VDS = 0 V VGS = -20 V, VDS = 0 V 30 ------0.03 ------1 10 100 -100 V V/C A A nA nA
On Characteristics
VGS(th) RDS(on) gFS Gate Threshold Voltage Static Drain-Source On-Resistance Forward Transconductance VDS = VGS, ID = 250 A VGS = 10 V, ID = 10 A VGS = 4.5 V, ID = 5 A VDS = 10 V, ID = 5 A
(Note 4)
1.0 ----
---16
2.5 0.0135 0.02 --
V S
Dynamic Characteristics
Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz ---980 590 145 1280 770 190 pF pF pF
Switching Characteristics
td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = 24 V, ID = 10 A, VGS = 5 V VDD = 15 V, ID = 5 A, RG = 50
(Note 4, 5)
-----(Note 4, 5)
30 165 65 110 21 4.2 12
70 340 140 230 28 ---
ns ns ns ns nC nC nC
---
Drain-Source Diode Characteristics and Maximum Ratings
IS ISM VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 2.3 A Drain-Source Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0 V, IS = 24 A, dIF / dt = 100 A/s
(Note 4)
------
---45 45
2.3 50 1.1 ---
A A V ns nC
Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 3mH, IAS = 10A, VDD = 15V, RG = 25 , Starting TJ = 25C 3. ISD 10A, di/dt 300A/us, VDD BVDSS, Starting TJ = 25C 4. Pulse Test : Pulse width 300s, Duty cycle 2% 5. Essentially independent of operating temperature
(c)2000 Fairchild Semiconductor International
Rev. A, May 2000
FQS4410
Typical Characteristics
I D, Drain Current [A]
10
1
ID, Drain Current [A]
VGS 10.0 V 8.0 V 6.0 V 5.0 V 4.5 V 4.0 V 3.5 V Bottom : 3.0 V Top :
10
1
150 25
10
0
Note : 1. 250 Pulse Test s 2. TC = 25
-55
10
-1
Note 1. VDS = 10V 2. 250 Pulse Test s
10 -1 10
0
10
0
2.0
2.5
3.0
3.5
4.0
V DS , Drain-Source Voltage [V]
VGS, Gate-Source Voltage [V]
Figure 1. Output Characteristics
Figure 2. Transfer Characteristics
40
Drain-Source On-Resistance
30
I DR , Reverse Drain Current [A]
VGS = 4.5V
10
1
R DS(ON) [m ],
VGS = 10V
20
10
0
10
150
-1
25
Note : TJ = 25
Note : 1. VGS = 0V 2. 250 Pulse Test s
0 0 10 20 30 40 50
10
0.2
0.4
0.6
0.8
1.0
1.2
ID, Drain Current [A]
VSD, Source-Drain voltage [V]
Figure 3. On-Resistance Variation vs. Drain Current
Figure 4. Source-Drain Diode Forward Voltage
3000
Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd
12
2500
10
VDS = 15V VDS = 24V
V GS , Gate-Source Voltage [V]
Coss
2000
8
Capacitance [pF]
Ciss
1500
Note ; 1. VGS = 0 V 2. f = 1 MHz
6
1000
Crss
4
500
2
Note : ID = 10A
0 -1 10
0 10
0
10
1
0
5
10
15
20
25
30
35
40
VDS, Drain-Source Voltage [V]
QG, Total Gate Charge [nC]
Figure 5. Capacitance vs. Drain-Source Voltage
Figure 6. Gate Charge vs. Gate-Source Voltage
(c)2000 Fairchild Semiconductor International
Rev. A, May 2000
FQS4410
Typical Characteristics
(Continued)
1.2
2.5
BV DSS , (Normalized) Drain-Source Breakdown Voltage
2.0
1.1
Drain-Source On-Resistance
R DS(ON) , (Normalized)
1.5
1.0
1.0
0.9
Note : 1. V = 0 V GS A 2. ID = 250
0.5
Note : 1. VGS = 10 V 2. ID = 10 A
0.8 -100
-50
0
50
100
o
150
200
0.0 -100
-50
0
50
100
o
150
200
TJ, Junction Temperature [ C]
TJ, Junction Temperature [ C]
Figure 7. Breakdown Voltage vs. Temperature
Figure 8. On-Resistance vs. Temperature
12
Operation in This Area is Limited by R DS(on)
10
2
10
100 s
ID , Drain Current [A]
1 ms
10
1
10 ms 100 ms
ID , Drain Current [A]
8
6
10
0
DC
4
Notes :
10
-1
1. TC = 25 C 2. TJ = 150 C 3. Single Pulse
o
o
2
10
-1
10
0
10
1
0 25
50
75
100
125
150
VDS, Drain-Source Voltage [V]
TC, Case Temperature []
Figure 9. Maximum Safe Operating Area
Figure 10. Maximum Drain Current vs. Case Temperature
(t), T h e rm a l R e s p o n s e
10
2
D = 0 .5
10
1
0 .2 0 .1 0 .0 5 0 .0 2
Note s : 1 . Z J A( t ) = 5 0 /W M a x . 2 . D u t y F a c t o r , D = t 1 /t 2 3 . T J M - T A = P D M * Z J A( t )
10
0
0 .0 1 s in g le p u ls e
Z
JA
10
-1
10
-4
10
-3
10
-2
10
-1
10
0
10
1
10
2
t 1 , S q u a r e W a v e P u ls e D u r a tio n [ s e c ]
Figure 11. Thermal Response
(c)2000 Fairchild Semiconductor International
Rev. A, May 2000
FQS4410
Gate Charge Test Circuit & Waveform
50K 12V 200nF 300nF
Same Type as DUT VDS
VGS Qg 5V Qgs Qgd
VGS
DUT
3mA
Charge
Resistive Switching Test Circuit & Waveforms
VDS RG
RL VDD
( 0.5 rated VDS )
VDS
90%
5V
DUT
Vin
10%
td(on) t on
tr
td(off) t off
tf
Unclamped Inductive Switching Test Circuit & Waveforms
L VDS VDD ID RG DUT VDD BVDSS IAS
BVDSS 1 EAS = ---- LL IAS2 -------------------2 BVDSS -- VDD
ID (t) VDS (t)
tp
10V
Time
(c)2000 Fairchild Semiconductor International
Rev. A, May 2000
FQS4410
Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT + VDS _ IS L Driver RG
Same Type as DUT
VDD
VGS
* dv/dt controlled by RG * IS controlled by pulse period
VGS ( Driver )
Gate Pulse Width D = -------------------------Gate Pulse Period
10V
IFM , Body Diode Forward Current
IS ( DUT ) IRM
di/dt
Body Diode Reverse Current
VDS ( DUT )
Body Diode Recovery dv/dt
Vf
VDD
Body Diode Forward Voltage Drop
(c)2000 Fairchild Semiconductor International
Rev. A, May 2000
FQS4410
Package Dimensions
8-SOP
MIN 1.55 0.20 0.061 0.008 0.1~0.25 0.004~0.001
#1
#8 4.92 0.20 0.194 0.008 5.13 MAX 0.202
( #4 #5 6.00 0.30 0.236 0.012
+0.10 0.15 -0.05 +0.004 0.006 -0.002
0.56 ) 0.022 1.80 MAX 0.071 MAX0.10 MAX0.004 3.95 0.20 0.156 0.008 5.72 0.225 0.50 0.20 0.020 0.008
(c)2000 Fairchild Semiconductor International
0~ 8
1.27 0.050
0.41 0.10 0.016 0.004
Rev. A, May 2000
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DOMETM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST(R)
DISCLAIMER
FASTrTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM POPTM PowerTrench(R)
QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM UHCTM
VCXTM
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Advance Information Product Status Formative or In Design First Production Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Preliminary
No Identification Needed
Full Production
Obsolete
Not In Production
(c)2000 Fairchild Semiconductor International
Rev. F1


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